金年会·(中国)_金年会

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The SLP74LVTH125 is a high performance bus buffer. The device is designed for 2.7V to 3.6V Vcc operation, but with the capability to provide TTL interface to a 5V system, This feature allows the use of these devices as translators in mixed 3.3V and 5V system environment.

The device has four independent line drivers with 3-state outputs. When the input of OE is high, the associated output is in the high-impedance state.


Main feature
  • Quadruple bus interface

  • Output capability: +64mA and -32mA

  • TTL input and output switching levels

  • Input and output interface capability to 5V systems

  • Live insertion and extraction permitted

  • No bus current loading when output is tied to 5V bus

  • Bus hold data inputs without need of external pull-up

  • or pull-down resistors

  • Power-up 3-state

  • ESD protection:

  • HBM  2000V

  • CDM  500V

  • Latch up performance: 100mA

  • Specified from -40°C to +85°C


Ordering Information
Product Name Package form Marking Hazardous Substance Control Packing Type Remarks
SLP74LVTH125EBTR SOP-14-225-1.27 74LVTH125 Halogen free Tape & Reel
Block Diagram

SLP74LVTH125.png

Documents
title Types of Size (KB) date Download the latest English version
SLP74LVTH125 0 1970-01-01 SLP74LVTH125 Brief Datasheet
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